Machine Learning Assisted Evolutionary Algorithm for Device-Circuit Multi-Objective Co-optimization of Actively Shielded MWCNT Interconnects

Journal article

K. Dimple, M. Ehteshamuddin, Avirup Dasgupta, Sourajeet Roy
Electrical Design of Advanced Packaging and Systems Symposium, 2024

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APA Click to copy
Dimple, K., Ehteshamuddin, M., Dasgupta, A., & Roy, S. (2024). Machine Learning Assisted Evolutionary Algorithm for Device-Circuit Multi-Objective Co-optimization of Actively Shielded MWCNT Interconnects. Electrical Design of Advanced Packaging and Systems Symposium.

Chicago/Turabian Click to copy
Dimple, K., M. Ehteshamuddin, Avirup Dasgupta, and Sourajeet Roy. “Machine Learning Assisted Evolutionary Algorithm for Device-Circuit Multi-Objective Co-Optimization of Actively Shielded MWCNT Interconnects.” Electrical Design of Advanced Packaging and Systems Symposium (2024).

MLA Click to copy
Dimple, K., et al. “Machine Learning Assisted Evolutionary Algorithm for Device-Circuit Multi-Objective Co-Optimization of Actively Shielded MWCNT Interconnects.” Electrical Design of Advanced Packaging and Systems Symposium, 2024.

BibTeX Click to copy

@article{k2024a,
  title = {Machine Learning Assisted Evolutionary Algorithm for Device-Circuit Multi-Objective Co-optimization of Actively Shielded MWCNT Interconnects},
  year = {2024},
  journal = {Electrical Design of Advanced Packaging and Systems Symposium},
  author = {Dimple, K. and Ehteshamuddin, M. and Dasgupta, Avirup and Roy, Sourajeet}
}

Abstract

In this paper, a neural network assisted evolutionary algorithm is developed to optimize the signal integrity features of multiwalled carbon nanotube (MWCNT) interconnects driven/loaded by nanosheet field effect transistor (NSFET) inverters in presence of active shielding. The key attribute of the proposed evolutionary algorithm is its ability to leverage analytic expressions of the multi-objective cost functions of the interconnects learned by neural networks and apply metaheuristic approaches to identify an optimal set of values of the design parameters of the NSFET devices and the signal and shield lines.